3rd February 2016
Posted By : Nat Bowers
Renesas Electronics has announced the development of 90nm one-transistor MONOS (Metal-Oxide-Nitride-Oxide-Silicon) flash memory technology that can be used in combination with a variety of processes, such as CMOS and bipolar CMOS DMOS (BiCDMOS), and provides high Programme/Erase (P/E) endurance and low rewrite energy consumption.
Renesas anticipates that the flash memory circuit technology will enable it to add flash memory to automotive analogue devices with improved performance and reliability. This superior circuit technology enables the industry’s first P/E endurance of over 100m cycles under a high junction temperature of 175°C, while also delivering low rewrite energy of 0.07mJ/8kB for low energy consumption.
One-transistor memory cells that allow the mixing of processes with fewer additional mask layers require application of a positive voltage to the memory cell selection gate during read operations. Also, a thinner charge-trapping film is necessary in order to achieve energy-efficient Fowler-Nordheim (FN) tunnelling during P/E operations. Both of these are factors that tend to reduce reliability under the high temperature conditions typical of automotive applications. To address this issue, Renesas has combined the one-transistor flash memory technology with the newly-developed array architecture technology that eliminates the need to apply a positive voltage during read operations to prevent reduction reliability under high-temperature conditions and assures the quality essential in automotive products. In addition, the newly developed one-transistor flash memory technology enables reduced power consumption during P/E operations.
As the performance of automotive analogue devices improves and the trend toward single-chip integration with MCUs continues, and the scope of applications expands from analog circuit tuning to include auto-fitting or data logging functionality, market demand for flash memory with greater P/E endurance is expected to increase. A newly developed Adaptable Slope Pulse Control (ASPC) technology enables generation of smoother rewrite pulses as a way to weaken electric fields that can degrade the characteristics of memory cells, boosting P/E endurance to over 100m cycles. The newly developed technology uses ASPC when applying rewrite pulses, monitoring the current value when pulses are applied and switching automatically to the optimal clock frequency. This lowers current consumption during P/E operations to a mere 98µA, which translates into a rewrite energy of 0.07mJ/8kB.
The newly developed Idling Programme Erase Management Unit (IPEMU) function enables the flash memory to control rewrites itself when the vehicle’s engine is stopped by a start-stop (anti-idling) system. This makes it possible to terminate the CPU and SRAM that activates the flash control and reduces power consumption during idle state by 99%.
By adopting these technologies, Renesas has developed 128kB flash memory prototypes employing 90nm one-transistor MONOS flash memory that successfully achieved the industry’s first P/E endurance over 100m cycles with a low rewrite current of 98µA. This rewrite current is two orders of magnitude smaller than previously achieved and translates into a rewrite energy of 0.07mJ/8kB.
The ability to easily add flash memory to devices employing a variety of processes, combined with low power consumption, is expected to also expand the range of possible IoT applications.